The present disclosure relates to circuit networks and, in particular, to a method of analyzing clock skew in a circuit network.
Circuit networks generally include a plurality of components or receivers coupled to a clock and receiving a clock input signal from a clock network. Due to various differences in clock path, receiver response and other parameters, the receivers tend to record different arrival times of the clock input signals and therefore produce output response signals in response to the clock input signals at different times. The difference between clock input arrival times at the receiver inputs is known as clock skew. In general, optimal network operation requires that clock skew be reduced or removed from the network or deliberately controlled in some particular fashion in order to meet specific design requirements.